`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:14:45 06/25/2023
// Design Name:   ADDER
// Module Name:   C:/Users/Administrator/Desktop/test/demo1/demo/TB_ADDER.v
// Project Name:  demo
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ADDER
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TB_ADDER;

	// Inputs
	reg clk;
	reg rst_n;

	// Outputs
	wire ld;

	// Instantiate the Unit Under Test (UUT)
	ADDER uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.ld(ld)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst_n = 0;

		// Wait 100 ns for global reset to finish
		#100;
      clk = 1;
		rst_n = 1;
		#100;
		clk = 0;
		rst_n = 0;
		// Add stimulus here

	end
      
endmodule

